Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic devices, called a field programmable gate array (FPGA), is popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory such as EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the configuration memory cells in the FPGA into which the bitstream is loaded then determine the function of the FPGA.
An important step in the manufacture of integrated circuits, such as CPLDs, FPGAs and the like, is testing these devices prior to shipment to a customer. However, chip handlers and testers are expensive, so chip designers have included test circuits on the devices (on the microchips) to reduce tester test time. Alternatively, test designers configure CPLDs and FPGAs to implement test designs to perform functions internally that can not be performed by a tester. This type of circuitry or configuration is known as “Built-In Self-Test” or “BIST”. U.S. Pat. Nos. 5,790,479, 6,005,829, 6,069,849, 6,144,262, 6,219,305, 6,232,845, 6,233,205, 6,356,514, and 6,452,489 describe how such structures are programmed and tested, and are incorporated herein by reference.
However, some tests still need to be done with a tester, especially analog characterization. One such area is input/output (I/O) duty cycle. Device operation is dependent upon proper I/O transistor operation. However, accurate performance measurement of I/O transistor operation is problematic. This is partly due to insufficient tester speed to measure I/O switching speed under operative conditions (“dynamic behavior”).
However, even with testers rated at the operational speed of microchips, accurate characterization of I/O transistor operation is elusive. Timing delays of leads and traces connecting the tester to the microchip are larger than some of the delays and periods being measured on the chip. Conventionally, parameters of I/O transistors are measured in a laboratory on a few sample chips to determine theoretical performance, which is then correlated with test data obtained from a tester on production chips. But it can take many hours of engineer and technician time to characterize and correlate less than ten microchips for just a few I/O transistors on each chip.
Though I/O transistors for each I/O are conventionally all made with the same semiconductor n-type and p-type processes for the chip on which they reside, differences among I/O transistors on a chip may exist. If duty cycle of an I/O is not within acceptable parameters, this can lead to catastrophic failure.
Accordingly, it is desirable and useful to be able to accurately characterize dynamic behavior of I/O transistors in a way that is less costly than previous approaches. Moreover, it is desirable to use dynamic behavior information for I/O transistor operation to shift operation away from failure, and, for more rigorous applications, to limit duty cycle.